The present invention relates generally to a semiconductor device and method of forming a semiconductor device, and more particularly, a method of forming a semiconductor device which includes performing an anneal to react a germanium-containing layer with a surface of a SiGe fin.
Vertical transport FETs (VFET) have potential advantages over conventional FinFETs in terms of density, performance, power consumption, and integration. First, the VFET provides for better density and allows scaling to sub-30 nm contacted poly pitch (CPP). Further, no diffusion break is required between devices, and nested devices have very high effective current (Ieff) density and low capacitance.
Second, the VFET provides for higher performance and/or lower power. The VFET provides for faster devices due to higher Ieff and also supports higher Vmax. Further, Lgate length is not limited by CPP so better device Ion v. Ioff. The Lgate may be about 15 nm, and can be longer or shorter if desired. Further, capacitance may be about comparable for isolated FETs, and VFET capacitance is lower for multi-finger devices than lateral FETs. The VFET also eliminates finFET width quantization (saves power by not over-sizing device width), has a large bottom S/D region to reduce lateral resistance, and a lower trench silicide (TS) resistance by eliminating top S/D TS. Further, FETs in series fins can avoid TS on both source and drain
Third, the VFET provides improved manufacturability and scaling. The VFET makes it easier to integrate multi-material stacked structures, provides TS to bottom S/D design flexibility, has a much lower aspect ratio for etch and fill, and provides better connectivity which allows relaxed TS, contact and M0 features.